Technical Field
The present invention relates generally to the field of electrostatic discharge (ESD) protection in silicon on insulator (SOI) integrated circuits. The present invention utilizes the xe2x80x9cfloating bodyxe2x80x9d of SOI devices to enhance circuit performance and ESD robustness.
MOSFET scaling on bulk silicon has been the primary focus of the semiconductor and microelectronic industry for achieving CMOS chip performance and density objectives. The shrinking of MOSFET dimensions for high density, low power and enhanced performance requires reduced power-supply voltages. Because power consumption, is a function of capacitance, power supply voltage, and transition frequency, the focus has been on reducing both capacitance and power supply voltage as the transition frequency increases. The components of the MOSFET capacitance consist of diffusion and gate capacitances. As a result, dielectric thickness and channel length are scaled with power-supply voltage. Power-supply reduction continues to be the trend for future low-voltage CMOS.
However, with power-supply reduction, transistor performance is severely impacted by both junction capacitance and the MOSFET body effect at lower voltages. As transistors continue to become smaller, short-channel effects (SCE) control, gate resistance, channel profiling and other barriers become an issue for advanced CMOS technologies. While significant success has been achieved with successive scaling of bulk CMOS technology, the manufacturing control issues and power consumption will become more difficult to deal with.
Using silicon-on-insulator (SOI) substrates, many concerns and obstacles of bulk-silicon CMOS can be eliminated at low power-supply voltages. CMOS-on-SOI has significant advantages over bulk CMOS technology and will achieve the scaling objectives of low power and high performance for future technologies. CMOS-on-SOI provides low power consumption, low leakage current, low capacitance diode structures, good sub-threshold I-V characteristics (better than 60 mV/decade), a low soft error rate, good SRAM access times, and other technology benefits.
SOI MOSFETs, in functional and ESD applications, are significantly different from standard bulk MOSFET structures. SOI transistor operation is dependent on the state of the SOI MOSFET xe2x80x9cbodyxe2x80x9d. The voltage potential of the SOI MOSFET body is dependent on the applied voltages of the gate, drain, substrate, source and the prior potential of the body. When voltages are applied to the gate, drain and source, competition between the competing capacitive elements from previous gate-to-body, drain-to-body, source-to-body, body-to-substrate, gate-to-drain and gate-to-source capacitances will determine the eventual potential of the body. The potential of the body modulates the threshold voltage of the transistor and influences the voltage needed on the gate to invert the surface and turn on the transistor. Forward biasing also occurs when the body voltage exceeds the source or drain voltage.
The xe2x80x9cbody effectxe2x80x9d in SOI is the modulation of the threshold voltage as a function of the body voltage. For a negative applied voltage on the body of an n-channel device, the threshold voltage increases. Allowing forward-biasing of the body-source junction, the threshold voltage drops. When the body voltage is biased positive, a xe2x80x9creverse body effectxe2x80x9d occurs where the MOSFET threshold voltage decreases.
The technique of body-coupling is used in standard SOI circuits to create a xe2x80x9cdynamic thresholdxe2x80x9d (DTMOS) device. In a DTMOS device, the body and gate are coupled. Examples of DTMOS devices are illustrated in FIG. 4 as p- and n-channel transistors 33,34. As the DTMOS gate and body voltage increases, the threshold voltage decreases. DTMOS transistors have a high transconductance and saturation current at a lower power supply voltage compared to standard SOI MOSFETSs. DTMOS devices inherently have a bipolar transistor integrated into the structure. The body contact serves as a base of the lateral npn formed by the SOI transistor. When the body voltage exceeds the emitter base voltage, the DTMOS transistor can be placed in bipolar forward active mode. DTMOS devices are suitable for both functional and ESD applications because there are no xe2x80x9cfloating bodyxe2x80x9d problems, no kink effect issues and no threshold stability concerns.
To achieve low leakage, an ideal MOSFET should have a high threshold when the device is xe2x80x9coffxe2x80x9d (Vgs=0 V). To achieve high performance, an ideal MOSFET should have a low threshold voltage when the device is xe2x80x9conxe2x80x9d (Vgs=Vdd). DTMOS provides both ideal characteristics; this advantage allows DTMOS to be extendable to ultra low sub-0.6 V power supply because of the low leakage at zero gate bias. DTMOS also has an the advantage of an ideal subthreshold characteristic of 60 mV/decade. In summary, DTMOS transistors provides improved subthreshold slope of 60 mv/decade, higher mobility, higher current drive in a low- and high-current regime, and can extend the power supply voltage to 0.6 V and below.
There is growing interest in the advanced semiconductor technology industry for electrostatic discharge (ESD) protection of CMOS-on-SOI technology. SOI ESD robustness interests will peak as the migration from bulk CMOS to CMOS-on-SOI becomes a reality and achieving industry-acceptable ESD results becomes mandatory.
Initially, in bulk silicon, a grounded gate transistor was used for ESD protection. This device is unstable as its breakdown voltage characteristic has a snap back voltage. Additionally, devices of this type are subject to second breakdown, that is an uncontrolled thermal breakdown of the device.
U.S. Pat. No. 4,423,431 to Sasaki introduced the idea of using a gate-coupled transistor as an ESD protection device. In Sasaki a protective transistor is connected between a gate of a protected internal transistor and ground. A gate of a protective transistor is connected to an input terminal. Thus, when an abnormal voltage occurs at the input terminal, the protective transistor turns on permitting the charges to be passed to ground.
Many devices and methods for providing ESD protection have been proposed for SOI. For example, U.S. Pat. No. 5,610,790 to Staab et al. teaches conducting an overvoltage from the input pad to a first voltage power rail. The overvoltage is then conducted through a cross power supply clamp to a second voltage rail. U.S. Pat. No. 4,989,057 to Lu discloses a transistor having a floating body which is used as an ESD protection circuit. However, because of the floating body, the breakdown voltage characteristic of this ESD device has a snap-back voltage and suffers from the same disadvantages as the grounded gate devices.
SOI ESD protection networks have already made considerable progress in achieving industry acceptable ESD protection levels. xe2x80x9cCMOS-on-SOI ESD Protection Networksxe2x80x9d by Voldman et al., pp. 291-301 EOS/ES/ESD, Symposium Proceedings, October 1996, describes recent advances.
From an ESD perspective, DTMOS has significant natural advantages. In DTMOS, with the gate and body connected, the gate-to-body voltage is zero, reducing the voltage stress across the dielectric. A DTMOS transistor has three terminals: the interconnected body and gate, the source, and the drain. Gate-coupled networks achieve superior ESD robustness in comparison to non-coupled networks because gate-coupled networks improve the current distribution and uniformity in multi-finger MOSFETs. Applying gate-coupling to DTMOS devices, body- and gate-coupling improvements can be realized. Conceptually, the rise in the body voltage acts as a feedback or trigger to lower the threshold voltage, which allows the gate coupling to trigger at a lower applied voltage. Gate-coupled DTMOS thus has the advantage of early turn-on, a higher current drive, uniform current distribution, and a high ESD metric. DTMOS can be used in bias networks, RC networks, or others to provide ESD robust circuit networks.
Recently, the SOI body/gate-coupled xe2x80x9cdiodexe2x80x9d and its use in SOI ESD protection circuits was introduced by S. Voldman et al. in xe2x80x9cDynamic Threshold Body- and Gate-Coupled SOI ESD Protection Networks,xe2x80x9d pp. 210-220, EOS/ESD Symposium Proceedings 1997, which is incorporated herein by reference. A body- and gate-coupled (B/G-C) DTMOS xe2x80x9cdiodexe2x80x9d has two terminals; the body, gate and drain of a MOSFET structure are connected as one electrode and the source as the second electrode. FIG. 3 illustrates n- and p-channel B/G-C SOI diodes 21,22. The B/G-C SOI diode has both diodic and DTMOS modes of operation. The B/G-C SOI diode can conceptually be thought of as a DTMOS device in parallel with a diode element. When the node that is connected to the drain, gate, and body increases positively, the gate and body voltage also increase. Concurrently, the body voltage increases causing a decreasing MOSFET threshold voltage, allowing for early turn-on of the MOSFET. Additionally, when the pad voltage rises above the body-to-source voltage, the body diode forward biases. The B/G-C DTMOS SOI diode has more current drive than the standard SOI diode because of the body-coupling and base-drive initiated in the parasitic bipolar transistor. In both the high-and low-current regimes, a body- and gate-coupled MOSFET has more current drive than a standard SOI MOSFET and a SOI MOSFET in a diode configuration. The B/G-C SOI diode differs significantly in its ESD operation compared to an SOI poly-bounded diode (SOI Lubistors) and a diode designed from SOI MOSFET transistors. There are several means of conduction in this SOI B/G-C DTMOS double-diode ESD network. There is a diode formed between each power supply and the pad; there is an n- and p-channel DTMOS; and there are npn and pnp bipolar elements. The advantage of the B/G-C SOI diode is that it uses both the diode action and the dynamic threshold voltage MOSFET action.
An apparatus and method for handling an ESD pulse which occurs on an SOI integrated circuit is provided. The present invention takes advantage of the fact that in SOI integrated circuits there is no true substrate and the bodies of the transistors are independent from each other. Therefore logic signals can be applied to the bodies of the individual transistors. A pad subject to an ESD pulse is coupled to a discriminating means. The discriminating means generates a signal when an ESD pulse occurs and the signal is provided to a body bias circuit.
According to one embodiment of the invention, an ESD protection circuit, which is connected to a rail, is connected in between the pad and the discriminating means. The ESD protection circuit is connected to the pad and the rail is connected to the discriminating means. The body bias circuit in this embodiment may be a driver which is coupled between the rail and ground. When an ESD pulse occurs on the pad, it is passed via the ESD protection circuit to the rail. The signal from the discriminating means is then applied to a body bias circuit which turns on, discharging the pad and rail to ground.
According to another embodiment of the invention, the pad is coupled to at least one device which is sensitive to an overvoltage event. A node is arranged between the pad and the at least one device. An ESD protection circuit is coupled between the node and a first power rail. The discriminating means is connected to the first power rail. When an ESD pulse occurs, a signal is sent from the discriminating means to at least the body of a body-biased core clamp. The core clamp is connected between a second power rail and ground.
According to another aspect of the present invention, current is conducted from a pad of an SOI integrated circuit to a discriminating means. The discriminating means determines when an ESD pulse occurs and applies a signal to at least a body of a transistor producing a change in a threshold voltage of the transistor.